FIG. 1 shows a prior art epitaxial silicon wafer 10 on which a complementary pair of metal-oxide-semiconductor ("MOS") transistors 12 and 14 are arranged as a CMOS circuit 16. Wafer 10 is referred to, therefore, as CMOS wafer 10.
CMOS wafer 10 includes a monocrystalline epitaxial silicon layer 18 that is supported by a monocrystalline silicon substrate 20 formed by the Czochralski method. Epitaxial layer 18 is lightly doped with boron at a concentration of 2.times.10.sup.14 to 2.times.10.sup.15 atoms/cm.sup.3 to form a p.sup.- -type material, and substrate 20 is heavily doped with boron at a concentration of 3.times.10.sup.18 atoms/cm.sup.3 to form a p.sup.+ -type material. It will be appreciated that epitaxial layer 18 and substrate 20 could alternatively be doped with phosphorus and antimony, respectively, to form n-type materials.
CMOS circuit 16 is formed in and on epitaxial layer 18. Transistor 12 is an n-channel field-effect transistor having a source 22a and a drain 24a coupled by respective n.sup.+ -type channels 26a and 28a to a gate 30a. A p.sup.+ -type guard ring 32a provides lateral isolation of transistor 12 in epitaxial layer 18, and a patterned insulating layer 34 of SiO.sub.2 provides isolation between source 22a, drain 24a, and gate 30a.
Transistor 14 is a p-channel field effect transistor having a source 22b and a drain 24b coupled by respective p.sup.+ -type channels 26b and 28b to a gate 30b. Channels 26b and 28b are positioned in an n-type well 36 formed in epitaxial layer 18. An n.sup.+ -type guard ring 32b provides lateral isolation of transistor 14 in epitaxial layer 18, and insulating layer 34 provides isolation between source 22b, drain 24b, and gate 30b.
The light dopant concentration is epitaxial layer 18 provides it with a resistivity desirable for conventional operation of CMOS circuit 16. Epitaxial layer 18 is formed on heavily doped substrate 20, however, to reduce the susceptibility of CMOS circuit 16 to a phenomenon called latch-up, as described by Borland et al. in Advanced CMOS Epitaxial Processing for Latch-Up Hardening and Improved Epilayer Quality, 27 Solid State Technology, No. 8, August 1984.
Latch-up is a destructive phenomenon in which CMOS circuit structures latch onto a bipolar or junction transistor operating mode. Latch-up occurs when a voltage applied to the CMOS circuit changes rapidly, such as when the power supply voltage is switched on. The changing voltage induces a junction displacement current that initiates latch-up when the current magnitude is greater than a threshold magnitude. The threshold current at which latch-up is initiated decreases as the rate of change of the voltage applied to the CMOS circuit increases.
Although it reduces the susceptibility of CMOS circuit 16 to latch-up, the heavy doping of substrate 20 is disadvantageous because it interferes with the measurement and precipitation of oxygen in substrate 20. Oxygen is an important impurity incorporated into silicon wafers to provide mechanical strength and to facilitate removal of metallic contaminants from the wafer. However, latch-up is such a serious problem in CMOS circuits that most epitaxial CMOS wafers continue to be manufactured on heavily doped substrates.